Joel Auernheimer

Education

• Master of Science in Electrical Engineering from Arizona State University, December 2000.
• Bachelor of Science with highest honors (summa cum laude) in Electrical Engineering from Arizona State University, May 1999 (3.96 GPA).

Work Experience:

Intel Corporation:

Analog Engineer, August 2005 to present; Electrical Design and Analysis / Packaging and Interconnects; Chandler, Arizona.

• Managed and performed power integrity analyses for Xeon and Itanium platforms
• Developed automation to support power integrity analyses and related processes

Signal Integrity Engineer, May 2004 to August 2005; Signal Integrity Team / Packaging and Interconnects; Chandler, Arizona.

• Managed PCI-Express projects and analysis for various enterprise platforms

Package Design Engineer, January 2001 to May 2004; Substrate Design Engineering / Assembly Technology Development; Chandler, Arizona.

• Substrate Design Engineering Desktop/Chipsets Manager
• Responsible engineer for various desktop and chipset packages, including Pentium IV packages
• Worked closely with a multi-disciplinary, cross-platform team to create high-performance, low-cost solutions for these packages
• Performed physical design, electromagnetic modeling, computer simulation, signal integrity, and power delivery optimization using novel methods and application of electromagnetic field solvers, circuit simulators, and transmission line theory
• Developed and transferred methodology to partners in desktop, enterprise, and mobile design teams
• Coordinated resources using project management software
• Participated in and led design efforts for various pathfinding products

Mayo Foundation:

Engineering Co-op, Summers of 1997, 1999, 2000; Special Purpose Processor Development Group; Rochester, Minnesota.

• Performed verification and studies of the w-element model (HSPICE) and a PSPICE model developed at Arizona State University
• Developed graphical user interfaces for engineering and lab software
• Analyzed and applied time-domain reflectometry methods and models with parasitics information to determine the differences between Tektronic and Polar network analyzers
• Developed mathematical methods, deembedding techniques, and code to convert S-parameters to transmission line parameters (RLCG)

Arizona State University:

Undergraduate Research Assistant, August 1997 to July 1999; Electronics Packaging Lab; Tempe, Arizona.
Graduate Research Associate, August 1999 to May 2000.

• Computer simulation and electromagnetic modeling of transmission lines
• Developed an adaptive meshing scheme for improving Weeks’ method for computing frequency-dependent impedance of conductors
• Studied and characterized signal integrity problems with an SMA connector launch off of a printed circuit board (subcontract with Motorola)
• Developed and coded a transmission line model with full control of frequency-dependent parameters for time- and frequency-domain analysis

Selected Academic Awards:

• University Graduate Fellowship
• Distinguished Senior in Electrical Engineering
• National Science Foundation Graduate Fellowship Honorable Mention
• Goldwater Science and Engineering Scholarship

Industry Recognitions:

• Young Engineer of the Year (IEEE Phoenix Chapter, 2008)
• Senior Member of the IEEE (2009)

Skills:

• General: Computer simulation, microwave circuit design, electromagnetic modeling, transmission line analysis, package design, simultaneous-switching noise, signal integrity, application development, software engineering, programming, project management
• Languages: C/C++, Java, VB, VBA, Perl, shell scripting, HTML, CSS, Python, PHP
• Software: Cadence tools (Advanced Package Designer (APD), Allegro), Ansoft tools (Q3D, HFSS), Matlab, HSPICE, LaTeX, PSPICE, Microsoft Office (Excel, PowerPoint, Word, Outlook, Project), Visio, Sharepoint
• Operating Systems: UNIX, Linux, Windows

Publications:

• Xingling Zhou, Joel Auernheimer, George Pan, and Barry Gilbert: “An Improved SPICE Compatible Model for Multiconductor Transmission Lines.” Published in IEEE CEFC ’98 The Eighth Biennial IEEE Conference on Electromagnetic Field Computation, June 1-3, 1998 in Tucson, Arizona, p. 363. (Abstract)
• Joel A. Auernheimer, “Streamlined Methods for Power Delivery Simulations,” Design and Test Technology Conference (Intel internal conference), July 2002.
• Joel A. Auernheimer and Farzaneh Yahyaei-moayyed, “Efficient and Flexible Power Distribution System Design and Analysis,” Design and Test Technology Conference (Intel internal conference), July 2003.
• Joel A. Auernheimer, “New Methods for Power Distribution System Design and Analysis,” Electronic Components and Technology Conference, June 2004.

Patents:

• Flex tape architecture for integrated circuit signal ingress/egress
• Array capacitor with resistive structure
• Array capacitor for decoupling multiple voltage rails
• Forming a substrate core with embedded capacitor and structures formed thereby
• Land grid array with socket plate
• Array capacitors for broadband decoupling applications
• Two other patents pending